rev. 0.1 copyright ? 2014 by silicon laboratories SI53108-EVB SI53108-EVB si53108 e valuation b oard u ser ? s g uide description the SI53108-EVB can be used to evalua te the si53108- a01agm, an 8-output pcie gen1/2/3 buffer that can operate in either fanout or zero delay mode. features ? 10-inch traces to evaluate signal integrity ? the signal traces of the input and outputs have a single-ended impedance of 50 ohms, and differential impedance of 100 ohms. ? the series resistance on the outputs are set to match to this impedance design. ? dc pin controls per data sheet specification. ? ability to measure input to output propag ation delay. ? ability to measure pcie clock jitter. ? ability to program features of si53108-a01agm via i 2 c interface.
SI53108-EVB 2 rev. 0.1 1. schematics figure 1. schematic 1 ? ?
SI53108-EVB rev. 0.1 3 figure 2. schematic 2
SI53108-EVB 4 rev. 0.1 figure 3. schematic 3
SI53108-EVB rev. 0.1 5 2. input and power supply sequencing the si53108-a01agm should be powered up with supply at both the vdd and vdd_io nodes (at the jumpers available on the evb). a 100mhz or 133mhz hcsl input cl ock should be applied to pins 8 and 9. there is no internal or on-board resistive terminat ion, therefore hcsl termination needs to be provided at the input if needed by the driver. the input clock should be applied only after the supplies are stable. 3. quick start guide: 1. enable supply on the vdd pin. 2. enable supply on the vddio pin. 3. apply input clock on the sma connectors clk_in/clk_in# and measure the return path clock on clk_in_ret, clk_in#_ret. figure 4. clock return path a. the input clock measured at j32, j33 needs a 50-ohm termination on the scope. b. the attenuation will be 1: 10 after the above terminati on. appropriate scaling (10x) needs to be set at the scope to adjust for the scaling. 4. the output clocks are now set up and can be measur ed on an oscilloscope or fr equency domain measurement instrument. 4. usage of the evb 1. once the evb has been set up, the following can be evaluated: 2. signal integrity of the device when driving 10-inch, 100-ohm differential traces. 3. effect of capacitance load on output signal integrity. 4. output-to-output skew over 10-inch traces. 5. input-to-out put prorogation delay in bypass, hbw, and lb w modes using the input clock return path. 6. measuring the power consumption of the device. 7. modification of the device settings via the i 2 c interface.
SI53108-EVB 6 rev. 0.1 5. bill of materials ?
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